module spt(
    input           clk_100m           ,
    input           rst_spt_n          ,
    
    input           cpuif_mode         ,
    input           cpuif_port_sel     ,
    
    output          spt_cpuif_head_err ,
    output          spt_cpuif_tail_err ,
    output          spt_cpuif_short_pkt,
    output          spt_cpuif_long_pkt ,
    output          spt_cpuif_ok_pkt   ,
    
    input           core_spt_cs_n,
    input           core_spt_we_n,
    input  [9:0]    core_spt_addr,
    output [23:0]   spt_core_rdata,
    input  [23:0]   core_spt_wdata,
    input           core_spt_wdata_oe_n,
    
    input           vid_in,
    input  [15:0]   data_in,
    output          vid_out,
    output [15:0]   data_out,
    
    output          SRAM_CS_A_N,
    output          SRAM_WE_A_N,
    output [9:0]    SRAM_ADDR_A,
    input  [23:0]   SRAM_RDATA_A,
    output [23:0]   SRAM_WDATA_A,
    output          SRAM_WDATA_OEA_N,
    
    output          SRAM_CS_B_N,
    output          SRAM_WE_B_N,
    output [9:0]    SRAM_ADDR_B,
    input  [23:0]   SRAM_RDATA_B,
    output [23:0]   SRAM_WDATA_B,
    output          SRAM_WDATA_OEB_N
);

wire         ram_w_en;
wire [15:0]  ram_w_data;
wire [10:0]  ram_w_addr;
wire         ram_r_en;
wire [10:0]  ram_r_addr;

wire         spt_a_cs_n = !(ram_w_en);
wire         spt_a_we_n = 1'b0;
wire [9:0]   spt_a_addr = ram_w_addr[9:0];

wire         spt_b_cs_n = !(ram_r_en);
wire         spt_b_we_n = 1'b1;
wire [9:0]   spt_b_addr = ram_r_addr[9:0];

spt_core u_spt_core(
    .clk_100m           (clk_100m),
    .rst_spt_n          (rst_spt_n),

    .spt_cpuif_head_err (spt_cpuif_head_err),
    .spt_cpuif_tail_err (spt_cpuif_tail_err),
    .spt_cpuif_short_pkt(spt_cpuif_short_pkt),
    .spt_cpuif_long_pkt (spt_cpuif_long_pkt),
    .spt_cpuif_ok_pkt   (spt_cpuif_ok_pkt),

    .vid_in             (vid_in),
    .data_in            (data_in),
    .vid_out            (vid_out),
    .data_out           (data_out),

    .ram_w_en           (ram_w_en),
    .ram_w_data         (ram_w_data),
    .ram_w_addr         (ram_w_addr),

    .ram_r_en           (ram_r_en),
    .ram_r_data         (SRAM_RDATA_B[15:0]),
    .ram_r_addr         (ram_r_addr)
);

assign SRAM_CS_A_N      = cpuif_mode ? spt_a_cs_n : 
                          !cpuif_port_sel ? core_spt_cs_n : 1'b1;
assign SRAM_WE_A_N      = cpuif_mode ? spt_a_we_n :
                          !cpuif_port_sel ? core_spt_we_n : 1'b1;
assign SRAM_ADDR_A      = cpuif_mode ? spt_a_addr : core_spt_addr;
assign SRAM_WDATA_A     = cpuif_mode ? {8'd0, ram_w_data} : core_spt_wdata;
assign SRAM_WDATA_OEA_N = core_spt_wdata_oe_n;

assign SRAM_CS_B_N      = cpuif_mode ? spt_b_cs_n : 
                          cpuif_port_sel ? core_spt_cs_n : 1'b1;
assign SRAM_WE_B_N      = cpuif_mode ? 1'b1 :
                          cpuif_port_sel ? core_spt_we_n : 1'b1;
assign SRAM_ADDR_B      = cpuif_mode ? spt_b_addr : core_spt_addr;
assign SRAM_WDATA_B     = core_spt_wdata;
assign SRAM_WDATA_OEB_N = core_spt_wdata_oe_n;

endmodule
